Low Power Fir Filter Design Using Truncated Multiplier

نویسندگان

  • A.Deepika
  • A.Bhuvaneswari
چکیده

-In this paper Low-cost finite impulse response(FIR) design are presented using the concept of faithfully rounded truncated multipliers. We jointly consider the effective of bit width and hardware resources without sacrificing the frequency response and output signal accuracy. Non-uniform coefficient quantization with proper filter order to minimize the cost of total area. Multiple constant multiplication/accumulation in a pipelined direct FIR structure is implemented using an improved version of truncated multipliers. Comparisons with previous FIR filter design approaches show that the proposed design achieve the best area and power results.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

High Speed and Low Power Implementation of FIR Filter Design using DADDA & WALLACE Tree Multiplier

The most area consuming arithmetic operations in high-performance circuit’s Finite Impulse Response (FIR) multiplication is one. We are using different types of multipliers to reducing the cost of effective parameters in FIR filter design. We use only truncated multipliers in design, by using these multipliers we consume some more area and power, and ineffective results in transposed form. The ...

متن کامل

Efficient VLSI Architectures for FIR Filters

The Finite Impulse Response (FIR) filters are widely used in many Digital Signal Processing (DSP) applications. For these applications, the low power, less area, high speed and low complexity FIR filter architectures are required. The researchers have proposed many FIR filters to meet the above design specifications. This paper is focused on the some efficient reconfigurable FIR filter architec...

متن کامل

Design of Area and Power Efficient FIR Filter Using Truncated Multiplier Technique

Low-cost finite impulse response (FIR) designs are presented using the concept of faithfully rounded Booth multipliers. We jointly consider the optimization of bit width and hardware resources without sacrificing the frequency response and output signal precision. Non-uniform coefficient quantization with proper filter order is proposed to minimize total area cost. Multiple constant multiplicat...

متن کامل

Low Power Digital FIR Filter Design Using Optimized Adder and Multiplier

This paper proposes a design of low power and low delay digital finite-impulse response (FIR) filter. Nowadays, there are many portable applications requiring low power and high throughput than ever before. Thus, low power system design has become a significant performance goal. The Finite Impulse Response (FIR) Filter is the important component for designing an efficient digital signal process...

متن کامل

Design of Digital Finite Impulse Response Filter Using Different Low Power Mulitipliers

Low Multipliers and Adders are used to reduce dynamic power consumption of a Digital Finite Impulse Response (FIR) filter. These methods include low power serial multiplier and serial adder, combinational booth multiplier, shift/add multipliers, folding transformation in linear phase architecture and applied to FIR filters to reduce power consumption and Distortion is also reduced. The proposed...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2014